1. Field of the Invention
This invention relates to semiconductor packaging technology, and more particularly, to an intercrossedly-stacked dual-chip semiconductor package and method of fabricating the same, which is designed specifically for the packaging of two semiconductor chips in one single package unit.
2. Description of Related Art
to Multi-chip packaging technology is used to pack two or more semiconductor chips in one single package unit, so that one single package unit is capable of offering a manifold level of functionality or data storage capacity. Memory chips, such as flash memory chips, are typically packaged in this way so as to allow one single memory module to offer an increased data storage capacity.
Related patents, include, for example, the U.S. Pat. No. 5,721,452 entitled xe2x80x9cANGULARLY OFFSET STACKED DIE MULTICHIP DEVICE AND METHOD OF MANUFACTURExe2x80x9d. This patent discloses an inventive semiconductor packaging technology that is designed for the packaging of two semiconductor chips in an offset die stacking arrangement to provide a dual-chip package.
The utilization of the foregoing patent, however, has several drawbacks. First, it requires the use of pillars to support the wire-bonding areas of the overlying chip, which would make the overall packaging process quite complex and thus costly to implement. Second, since the overlying chip is not coupled to die pad, it would make the finished semiconductor package poor in heat-dissipation efficiency. Third, since the stacked chips are adhered to each other by means of an adhesive layer, they would be easily subjected to delamination, resulting in reliability problem to the finished semiconductor package.
It is therefore an objective of this invention to provide a new dual-chip semiconductor packaging technology, which can be fabricated without having to use pillars to support the wire-bonding areas of the packaged semiconductor chips.
It is another objective of this invention to provide a new dual-chip semiconductor packaging technology, which allows the packaging process to be implemented in a less complex and more cost-effective manner.
It is still another objective of this invention to provide a new dual-chip semiconductor packaging technology, which allows the packaged semiconductor chips to have an increased heat-dissipation efficiency.
It is yet another objective of this invention to provide a new dual-chip semiconductor packaging technology, which can be implemented without having to adhere the packaged semiconductor chips to each other so as to prevent delamination problem.
In accordance with the foregoing and other objectives, the invention proposes an intercrossedly-stacked dual-chip semiconductor package and method of fabricating the same.
The semiconductor packaging technology according to the invention is characterized by an intercrossedly-stacked dual-chip arrangement which is constructed on a specially-designed leadframe having a supporting frame; a die pad supported on the supporting frame and having a peripherally-located upper portion and a centrally-located downset portion; and a set of leads linked to the supporting frame and arranged around the die pad. A first semiconductor chip is mounted within the downset portion of the die pad, while a second semiconductor chip is mounted on the upper portion of the die pad in an intercrossedly-stacked manner in relation to the first semiconductor chip.
Since the invention requires no pillars in the dual-chip structure, it allows the packaging process to be implemented in a less complex and more cost-effective manner than the prior art. Moreover, since the underlying chip is attached to die pad, it allows an increased heat-dissipation efficiency to the package. In addition, since the invention can be implemented without having to adhere the two chips to each other, it can help prevent delamination problem. The invention is therefore more advantageous to use than the prior art.